1. The exam is sequential (one-way) except for the last 5 minutes, during which it becomes free navigation.
2. You must submit the answers to 3 questions every 10 minutes.
3. During the last 5 minutes, you are only allowed to modify the answers to a maximum of 2 questions.
PARA-A. Datapath component latencies:
| Component | Latency |
|---|
| Register file | 200 ps |
| ALU | 250 ps |
| PC register (clock to Q) | 100 ps |
| Pipeline register (inter stage buffer) - pipelined processor only | 50 ps |
| WB output multiplexer | 50 ps |
PARA-B. Instruction mix:
| Type | Mix Percentage |
|---|
| R type | 40% |
| Beq | 20% |
| Lw | 25% |
| Sw | 15% |
PARA-C. Branch Sequence C:
(NT, T, T, NT, T, NT, T, NT, NT, T)
PARA-D. Branch Sequence D:
(NT, T, T, NT, NT, T, T, NT, T, T)
PARA-E. Pipeline conventions:
Refer to standard 5-stage MIPS pipeline:
• V1 = RegWrite signal (entering ID stage / Register file write)
• V2 = RegDst mux control (EX stage)
• V3 = MemtoReg mux control (WB stage)
• V4 = ALUSrc mux control (EX stage)
• V5 = MemRead signal (MEM stage)
PARA-F. Assembly Loop Code:
The following code is executed on the 5-stage pipelined processor presented in class and similar to the one in the figure above. (Assume the initial content of $s2 is equal to 0x10000.)
Loop: lw $t0, 0($s0) // $t0 = R8
slt $t1, $t0, $zero
sb $t1, 0($s1)
addi $s0, $s0, 4 // $s0 = R16
addi $s1, $s1, 1
addi $s2, $s2, -1
bne $zero, $s2, Done
Done:
Recall that the forwarding selection is set to 10 when the dependency is on an instruction in the MEM stage, and to 01 when the dependency is on an instruction in the WB stage.